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VHDL HART Modem with 32.768 kHz Clock
By Analog Services, Inc.
Here's an easy way to design your own HART modem by
downloading a VHDL file. This is a "digital-only"
type of modem that works similarly to the Symbios 20C12 and Smar HT2012. You will
need to add your own analog functions to get a complete modem, just as you do with the
Symbios and Smar chips. For information on the analog parts you need to add, see
our HART Application Note.
The HART modem described here uses a 32.768 kHz clock, which means that you may be able to get by with a very cheap (currently about 15 cents each in volume) wristwatch-frequency crystal. In contrast, most HART modems currently available require a clock of at least 460.8 kHz. Using a 32.768 kHz clock, this modem generates FSK shift frequencies of 1199 Hz and 2198 Hz. These are close enough to the desired frequencies that the clock tolerance can be almost 1%. Of course you can still use higher frequency clocks by dividing them down. As examples, you can use 460.8 kHz divided by 14, 1.024 MHz divided by 31, or 3.58 MHz divided by 109.
One difference between this modem and Symbios or Smar modems is that the modulator and demodulator are both operating all of the time. A loopback function is also provided so that the modulator output can be fed directly back to the demodulator input for testing. The /RTS input doesn't select between modulator and demodulator operation. All it does is control the Hi-Z state of the modulator output.
The modem has been implemented in a Cypress 37128 CPLD and tested. Test results are presented below. The Cypress part in a 100 pin quad flat pack is less than $12 (based on information from Unique Technologies). The Cypress CPLD isn't a low-power device. So you won't get as low a current consumption with it as you would with either the Symbios 20C12 or Smar HT2012.
The download file is named "modem1.zip". When you unzip this file you should extract these files:
1. "modem1.vhd", the VHDL source code.
2. "modem1.jed", the file to program a Cypress 37128 CPLD device.
3.
"lp_rand.awf", a waveform file. The content of this file is explained
below.
Modulator Operation
A block diagram of the modulator is shown in figure 1.
Figure 1 -- Modulator Block Diagram
It uses a numerically controlled oscillator (NCO) with a modulus of 164 and load
values of 6 (for 1200 Hz) and 11 (for 2200 Hz). The oscillator uses the system clock
frequency of 32.768 kHz. The decoder has a single output. It is high for input
values of 82 to 163 and low for input values of 0 to 81.
Demodulator Operation
HART uses FSK, which means that the information is contained in the time between zero crossings of the carrier signal. Before the carrier signal reaches the demodulator it is normally converted to a logic level by applying it to a comparator. The comparator output is applied to the RXA input of the modem, and consists of a square wave with varying length of time between transitions.
The demodulator block diagram is shown in figure 2.
Figure 2 -- Demodulator Block Diagram
The demodulator samples RXA at the clock frequency of 32.768 kHz. When the lower frequency is present, the number of samples per half cycle of carrier is 13.65. When the upper frequency is present, the number of samples per half cycle of carrier is 7.45. The integer range that just overlaps these values is 7 to 14. Noise present on the carrier can shift the zero-crossings of the signal and extend this range to 6 to 15. Thus, the incoming samples will range from 6 to 15 ones followed by 6 to 15 zeros, followed by 6 to 15 ones, etc. Noise can also cause multiple transitions of the comparator output at a given zero crossing. These can lead to an extra one being inserted into a string of what should be all zeros or an extra zero being inserted into a string of all ones. These extra ones and zeros are suppressed as described below.
The edge detector finds the zero-crossings of the carrier signal by looking for a change from zero to one or from one to zero at RXA. The edge detector looks at two successive samples and generates a one if they are different and a zero if they are the same. The edge detector output is applied to a 15-stage shift register clocked at the sample rate of 32.768 kHz. Thus, the shift register content is mostly zeros with an occasional one representing a carrier zero-crossing. The number of zeros between the ones in the shift register is a measure of the incoming FSK frequency.
The shift register content is continuously examined by decoder 1, whose output is fed back and controls the switch at the shift register input. The switch can select a logic zero, a logic one, or the edge detector output. The normal position of the switch is the edge detector output. If decoder 1 detects that the shift register is about to become empty of ones, it inserts a one into the shift register in place of the edge detector output. This is done to insure correct operation of subsequent parts of the demodulator. It also serves as a substitute 1200 Hz carrier signal to keep RXD high (idle state) when there is no carrier present. (The actual frequency of this pseudo-carrier is slightly less than 1200 Hz.) A second purpose of decoder 1 is to prevent noise effects from reaching the shift register. If the decoder finds that there is a one in any of the first 5 positions of the shift register, it will force a zero into the shift register in place of the edge detector output. This insures that there will be at least 5 zeros between ones in the shift register and effectively removes any extra ones due to noise.
The ones in the shift register can be separated by 5 to 14 zeros, depending on the incoming signal frequency. The number of zeros between ones effectively indicates which frequency is present during the time that it is present. A second decoder, decoder 2, determines what frequency is present by generating a 3-bit number based on the number of zeros between ones. The decoder 2 input and output are shown in the following table:
Shift Reg Zeros Value
Frequency
of Decoder 2
Represented by
Decoder 2 Value
6 or fewer
0
2341 Hz
7
1
2048
8
2
1820
9
3
1638
10
4
1490
11
5
1365
12
6
1260
13 or more
7
1170
The output of decoder 2 is valid only when a one reaches the end of the sample shift register. At this time, the output of decoder 2 is clocked into a 3-bit "Interval Hold" register. Thus, the Interval Hold register is updated on each zero-crossing of the carrier and retains its value until the next zero-crossing. The number in the Interval Hold register represents the frequency that was present between these two zero crossings.
The Interval Hold register output is applied to a "rolling average" filter with sample rate of 32.768 kHz. The filter increases the frequency resolution (reduces the quantization error). It also increases the effective sample rate for changes in frequency. (The unfiltered frequency value only changes twice per cycle of the carrier.) Without filtering, the RXD value (demodulator output) would have excessive jitter. The rolling average is the best that can be done without resorting to a full multiply-accumulate type of digital filter. Simulations show that a 16 stage filter is sufficient to reduce RXD jitter to about plus and minus 11% of one bit time (1 bit time = 1/1200 second).
The operation of an ideal filter will be explained first. This is followed by an explanation of how the filter is modified to arrive at the practical filter of figure 2. The minimum and maximum values of filter output are 0 (representing 2341 Hz) and 7 x 16 = 112 (representing 1170 Hz). The decision point is the geometric mean of 1200 Hz and 2200 Hz. This corresponds to the number 49 at the filter output. If the filter output is 49 or larger, then RXD is set to one, else it is set to zero. In principle this is how the demodulator works. However, the filter is limited by practical considerations so that its implementation is somewhat unconventional.
Because there are no clock cycles between filter samples, updating the filter output at each sample implies that the filter taps can only be added by using a giant decoder with 48 inputs (filter shift register is 3 x 16) and 7 outputs. But this is too large for a practical implementation. A well-known software technique for implementing a rolling average is to first observe that only two numbers change at every sample time and the rest are just shifted one position. This implies that the adder can still be implemented with an accumulator. Once each sample time, the number at the front of the Filter Shift Register is added to the accumulator and the number at the end of the Filter Shift Register is subtracted. This uses far less hardware than the giant decoder. But it also creates another problem: the initial value of the accumulator is not determined. Its value could constitute an offset, such that the reference value of 49 for determining RXD is incorrect.
A way around this is to let the accumulator establish its own initial value. If we limit the accumulator so that it can't go below 0 or above 112, it establishes its own initial value within a relatively short time. If the filter becomes loaded with all 7's, and the accumulator is limited to 112, then the accumulator will forever agree with the shift register content. But how does the shift register become loaded with all 7's? When there is no carrier, an artificially low carrier frequency is created as explained above. This causes the filter shift register to become loaded with all 7's. As it happens, even if the shift register never quite makes it to all 7's, the small offset that results doesn't appear to have much of an effect.
The actual implementation of the filter uses a 7-bit
accumulator and a number range of 8 to 120 instead of 0 to 112. And the reference
point for deciding RXD is 56 instead of 49. That is, the numbers are ideally offset
by 8 so that only positive numbers are ever used. 56 is used as the RXD reference
instead of 57 because 56 is an easier number to decode. Actually, all 3 numbers 8,
120, and 56 are chosen because they are easily tested without a large amount of
combinational logic. In binary they are 0001000, 1111000, and 0111000. If the
accumulator number is less than 8, then the upper 4 bits will all be 0. If the
accumulator is 120 or greater, then the upper 4 bits will all be ones. And if the
accumulator is less than 56, then bits 3, 4, and 5 will not be all ones.
Pin Description Using ____ CPLD
Simulation Data and Test Results
A portion of a MATLAB simulation of the demodulator using random input bits is given in figure ___. The plot shows the original data (input data), the Interval Hold value (pre-filter signal), the filter output (post-filter signal), and the demodulator output.
Figure
The "input data" in figure ___ has been deliberately shifted in time with respect to the other 3 plots for clarity.
Another MATLAB simulation was done to assess jitter. To do this, the outputs of 100 simulations were superimposed. Input to the modulator is random. This effectively creates multiple transitions at each bit time. A small section of the result, shown in figure ____, indicates that jitter in RXD is a small fraction of one bit time.
Logic simulations of the demodulator using the simulator that ships with the WARP package were also performed. Figure ___ below shows the logic simulation output added to a plot of the input + MATLAB simulation output. The time relationships are not to scale and are set for convenience in observing and plotting the waveforms.
The Logic Simulation output shown in figure ___ is a portion of
a larger simulation output. The full simulation output, which is 120 millisecond or
about 144 bits, is available in the file "lp_rand.awf". This is one of the
files that is produced from the "modem1.zip" download file. The waveforms
contained in lp_rand.awf can be viewed using the "open waveform" dialog in the
simulator supplied with the Cypress WARP package. The simulation that produced the
lp_rand.awf file is done at 100 times normal speed to accommodate the simulator.
Consequently it will show up as only 1.2 millisecond of data. And the clock
frequency will be 3.2768 MHz and one bit time will appear to be only 8.33 microsecond.
The simulation uses random input bits. It applies them to the TXD input of
the modem. The modem is set to loopback so that the modulator output (TXA) will be
applied directly to the demodulator input (RXA). The two waveforms in lp_rand.awf
are TXD (upper) and RXD (lower). The two waveforms show RXD delayed from TXD by
almost exactly one bit time.
Acknowledgement
We gratefully acknowledge the assistance of the following people and organizations in creating this modem. Assistance in using the WARP VHDL compiler was provided by Q. James Lie of Cypress Semiconductor. Sample parts were supplied by Anthony Leali, Area Account Manager of Unique Technologies (651-636-8432), and programmed by Rick Harding of Cypress Semiconductor.
References
1. WARP 5.2 CPLD Development Kit, Cypress Semiconductor.
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