Is There Life After HART?

4800 BPS HART:  A Proposal

by Analog Services, Inc.

    HART is the de facto communication standard for analog (4-20 mA) process instruments.  However, the common HART physical layer speed is 1200 bits/second (bps), which is too slow for some applications.  Various ways to increase speed have been discussed and investigated but have yet to be implemented.  Some of these also have drawbacks of  non-constant envelope, or need for greater bandwidth than existing HART, or need for relatively complicated (and current-consuming) modulation-demodulation.

    We present a new method that is relatively simple and yields a 3X to 4X speed increase.  The proposed method is a form of coded NRZ at 4800 bits/second.  In contrast to the FSK used in existing HART, this is a baseband method.   It uses about the same frequency band as existing HART and can work at about the same noise level.   In devising the new method we sought to minimize the changes that would be needed in HART Field Instrument hardware and software.  The major change is a different "modem".  Everything else stays about the same.  Software changes are minor, so that the existing software investment is protected.

Contents:

1.  Introduction and Overview
2.  Transmission
3.  Reception
4.  Highpass Filters
5.  Error Rate and Simulations
6.  Modem Chip Requirements
7.  Conclusion

On-Line Appendices:

Software & System Considerations
Coding
Characteristics of the FASTHART Channel
     and Proposed Specification Changes
Bit Error Rate

1.    Introduction and Overview

    The current speed of HART communication over analog process loops is 1200 BPS -- the same as when it started back in the late 1980s.  This is fast enough for some applications.  For others it is a source of aggravation but still acceptable.  And for others it just isn't fast enough.  Most people agree that a faster HART would be nice.  But they are wary of what it might cost.  There are two kinds of costs.  One is the cost of new product development.  Increasingly, this translates into software development cost.  The other cost is in terms of poorer performance or loss of flexibility.  That is, does a faster HART still work under all of the same circumstances as existing HART?

    Suppose we want a faster HART that minimizes product development costs and works wherever existing HART does.    What form would it take and how fast could it be?   We present here a possible answer in the form of a 4800 bits/second method that is nearly a "drop-in" replacement for existing HART.  It imposes few restrictions on end-users and is easily implemented by control equipment vendors.  Although it is probably still not as fast as some would like, it may be the best combination of fast, cheap, and flexible.

    Here is an overview of what we call "FASTHART".  It includes links to some of the more in-depth stuff.  As part of our proposal, we did a lengthy analysis of FASTHART and we'll show you some of the results.

    What Should A Faster HART Be?

1.    Software should stay the same or nearly the same, protecting a huge investment.

2.    Hardware should stay the same and operate the same, with at most a different
"modem" chip.

3.    FASTHART should work over existing networks (same wiring, same components).

4.    FASTHART should be backward compatible and coexist with existing HART.

    Keeping existing software means that the message frame format stays the same.  The communication is also UART-based, albeit at the higher speed of 4800 bits/second.  Arbitration and other timers remain the same.  The proposed method essentially replaces the communication between the two UARTs with a signal that is compatible with the existing line interfaces and existing network, as shown below.

Figure 1.1 -- FASTHART and how it Fits Into Existing Scheme

    In FASTHART nearly everything is the same as before, except that messages take less time.  That is, the amount of time that a given device asserts its carrier on the network is shorter.  Since inter-message gaps are the same, the resulting speed increase is not a full 4 times.  But it can still be significant (see box below).

Obviously, the software can't remain exactly the same.  Click here for a look at the things that need to change and some potential problems.

    The FASTHART signal consists of coded NRZ, illustrated in figure 1.2.  Normal NRZ has potentially long sequences of the same bit (long run length) and is not suited to the AC coupling that is needed in HART networks and devices.  Using coding, the long sequences are eliminated.  The price of coding is that more bits need to be transmitted.

Figure 1.2 -- Coded NRZ Signal
Longest Allowed Sequence of Same Bit is 3

But existing HART uses 11 bits to represent only 8.  One of the remaining 3 is a parity bit, which is needed for error control.  The other two bits, the UART start and stop bits, are excess baggage to make the receiving UART happy.  As long as it is fed these bits, the receiving UART doesn't care whether or not they actually appeared on the network.  This fortunate circumstance, of representing 8 bits with 11 bits, means that a coded NRZ signal can substitute for existing HART.  The exact code used is arbitrary.  The important thing is that there are more than enough 11-bit code words to represent 8 bits and still provide error control (parity).  Coding is discussed in more detail and a proposed code is given in a separate document.  Click here to view.

    Coded NRZ is used extensively in data communication.  One of the benefits of coding in FASTHART is that there are codes left over that can be used as unique preambles and start delimiters.  A weakness of existing HART is that the start sequence is indistinguishable from normal data.  FASTHART doesn't have this problem.

    The coding is chosen so that the longest group of identical bits is only 3.  This reduces the low-frequency content of the signal.  It also provides a sufficient transition density for receiver sync.  A rough idea of the frequency content is gained by noticing that alternating 1's and 0's correspond to 2400 Hz and the repeated sequence of 111000111000 ... corresponds to 800 Hz.   Thus, the frequency range of FASTHART is roughly 800 Hz to 2400 Hz.  This is comparable to the 1200 Hz and 2200 Hz of existing HART and explains why FASTHART has a similar power spectrum to HART and why it can be used on the same network and with the same line interface components.  The FASTHART spectrum is somewhat wider than HART, which leads to a few problems at the low-frequency end.  These are discussed later.  The actual FASTHART signal applied to the network would include shaping to limit the risetime.  This is not shown in figure 1.2.

    FASTHART is essentially synchronous communication, as opposed to the asynchronous communication of existing HART.  A clock recovery circuit is required as part of the receiver.  Existing HART allows gaps or idle time between characters.  In synchronous transmission gaps or idle time aren't defined.  Generally, a device transmitting FASTHART must be able to keep up with the 4800 bps rate.  In most modern HART devices this probably is not a problem.

    It might seem that clock skew between the system clocks in the transmitter and receiver would be a problem.  However, the clock recovery circuit in the receiver allows the receiver to simply replicate (in terms of timing) what was transmitted and present the replica to the receiver's UART.   The result is that the skew between the system clocks (UART clocks) occurs only within individual characters, just as in existing HART.

    Not that there aren't some timing problems.  The multiple conversions between serial and parallel data and the resulting delays are a particular challenge.  These are dealt with in detail below.

    FASTHART is polarity-dependent, while HART is not.  But this is easily dealt with in the receiver by generating both polarities and picking the one that gives the correct start-up sequence -- a common practice in data communications.

    From a communication theory viewpoint, increasing the bit rate by a factor of 4 without any other changes doesn't seem reasonable unless the existing noise level is relatively low.  In fact it is low.   Existing HART implementations often use a bandwidth of 10 kHz or more (compared with the 1200 Hz bit rate) and are able to do so because noise is low.   The proposed method uses integrate-and-dump detection to effectively limit bandwidth; along with an increase in minimum transmitted signal.  MATLAB simulations are used to show that the proposed method has an acceptable error rate.

    Not all of the details of the proposed method have yet been worked out.  In particular, a PLL is needed to synchronize a receive clock to the incoming data.  We simply assume that this PLL exists, is perfectly synchronized, and contributes no noise.  Our primary purpose is to present the method, identify likely impairments, and show that BER remains OK.

     Part of the proposed method involves changes to existing HART specifications.  The upper limit on the network resistance would be reduced from 1100 ohm to 600 ohm and the minimum transmit level would be increased by 25%.  These changes are believed to have almost no effect on existing HART operation and installation practices.  Click here to view reasons and justifications for these proposed changes, along with a complete discussion of the FASTHART channel and FASTHART requirements.

2.    Transmission

    A block diagram of the transmit path is given in figure 2.1.  Assuming that high speed is being used, the UART output is converted back to parallel.  The start, stop, and parity bits are stripped and the resulting 8 bit words are applied to an encoder.  The 11-bit encoder output is then converted to serial and applied to the shaper (includes D/A converter).   The shaper output is applied to an equalizer.  The equalizer output is applied to the line interface which drives the HART network.  The equalizer cancels the highpass coupling effects, if any, in the line interface.  It is dependent on the line interface design and applies mainly to HART Masters.  This is described later in greater detail.

Figure 2.1 -- Transmit Block Diagram

The encoder output LSB is fed back so that there are 9 inputs to the encoder.  As explained in the document on coding, this prevents two adjacent code words from producing a long same-bit sequence.

    Notice that the serial-to-parallel converter simply negates the UART function.  This is a wasteful, but necessary, step in the transmission process.  A similar wasteful step occurs at the receiver.  Future devices with parallel input and output might avoid this.   But our main consideration is that the device vendor be able to easily incorporate the new modem chip.  A parallel interface might preclude this.

    To preserve timing to the greatest extent possible, the FASTHART "Signal Out" should start at about the same time that there is a start bit at "UART Out".  But normally we wouldn't know what to send until the "Serial-to-Parallel" converter is loaded.  This is the purpose of the "Preamble Autoload" block.  On detection of the first start bit after RTS (request-to-send), the "Parallel-to-Serial Converter" is loaded with a FASTHART preamble character so that transmission of FASTHART begins immediately.  This is illustrated in figure 2.2.

Figure 2.2 -- Transmit Start-up

This adds an extra character to the message stream that has not yet been taken into account.  The extra character will decrease throughput slightly.  It also provides a longer preamble for receiver sync.   It does not affect any system timers or the Master arbitration, since these already have to accommodate messages of varying sizes.

    Another function of the transmitter that isn't shown is to distinguish between arriving 0xff characters that are supposed to be converted to FASTHART preambles and 0xff characters that are data.  A state machine that tracks the various transmitted fields in a message is capable of doing this.

3.    Reception

    The receive path diagram is shown in figure 3.1.

Figure 3.1 -- Receive Block Diagram

    The received signal is applied at "Signal In".  The Off-chip highpass filter is needed to reduce the signal + interference to a level compatible with the supply rails.   (For more information on the HART/FASTHART Channel, click   here   ).  Further signal processing is done digitally.  The signal is sampled at 57.6 kHz, which means that there are nominally 12 samples per bit.  Further highpass filtering is done digitally as explained below.   The output of the highpass filter is applied to the clock recovery and integrate-and-dump block.  The recovered clock is more or less a gate for the integrate-and-dump.  The integrator of the integrate-and-dump is cleared at the start of a bit and its output is read at the end of the the bit.

    The integrate-and-dump output is a the coded serial bit stream.  This is applied to a preamble detector, a start-delimiter detector, and the Serial-to-parallel Converter.   The start delimiter detector determines where a data word starts or stops so that the Serial-to-parallel Converter can be loaded at the correct word boundaries.  The output of the Serial-to-parallel Converter is the 11 bit FASTHART word.  It is applied to a decoder.  The decoder output is a 9 bit word representing the HART byte + odd parity.  This is applied to a FIFO as explained below, followed by a Parallel-to-Serial Converter that adds start and stop bits (a UART). 

    The proposed method uses two special non-data characters as preamble characters.  These are 01010101010 (decimal 682) and 10101010101 (decimal 1365).   These are deliberately excluded from occurring in normal data.  The two preamble words are alternated so that the FASTHART preamble consists entirely of alternating ones and zeros.   The number of preamble words transmitted depends on how many HART preamble characters are transmitted.  A start delimiter immediately follows the preamble.  Since HART uses any of several start delimiters, the FASTHART receiver must decode them and pass them through as data.

    The receiver also uses the coded start delimiter for word synchronization.  Therefore, it must recognize all code words that are start delimiters.  Word synchronization is a two-step process that begins with determining that a preamble is occurring.  The receiver looks for a specific 19-bit pattern of alternating 1's and 0's; namely the pattern 0101010101010101010.  For the proposed coding (click   here  to view section on coding), it can be shown that this pattern does not occur in normal data.  Once the receiver knows it is in the preamble it can begin looking for the start delimiter.  Upon receipt of a start delimiter, the start and end of each word is known.

    The alternating ones and zeros of the FASTHART preamble are a 2400 Hz tone that is used to synchronize a clock recovery PLL and to differentiate between HART and FASTHART.  The preamble of HART is primarily a 1200 Hz tone.

    Once it is determined that a FASTHART message is arriving and a preamble has been detected, some indeterminate time will occur until the start delimiter is recognized.  During this time, the modem loads the FIFO with one HART preamble character for every 11 bits of FASTHART preamble received.  When a start delimiter is finally recognized, it is decoded and immediately placed into the FIFO.  Thus, the FIFO absorbs timing differences prior to word sync.

4.    Highpass Filters

   The highpass filter requirements for FASTHART are given in a separate document describing the FASTHART channel.  (Click   here   to view.)  Highpass filtering is particularly destructive to FASTHART due to its frequency component down near 800 Hz.  In this section we illustrate what this filtering does to the signal and propose solutions. 

4.1     Receive Highpass

    The highpass filter built into the receiver removes analog signaling.  The requirements suggest a relatively simple implementation consisting of an off-chip continuous single-pole filter at 224 Hz followed by an on-chip digital filter equivalent to a single pole at 224 Hz.  This simultaneously satisfies the need for an overall attenuation slope of 40 dB/decade at 224 Hz and an off-chip filter with response that is down by at least a factor of 7 at 25 Hz.  (In fact the attenuation of the off-chip filter at 25 Hz would be about 224/25 = 9.)  But the result of applying these two filters is shown in figure 4.1.

Figure 4.1 -- Effect Of Receive Highpass Filters
Lower Trace = Input, Upper Trace = Output

The filter input consists of a random bit stream that has been encoded according to the proposed encoding rules.  Then it is trapezoidally shaped.  It is applied first to a continuous single-pole lowpass receive filter at 10 kHz.  (This is a filter that is commonly used for existing HART.)  It is followed by a continuous single-pole highpass filter at 224 Hz.  Then it is sampled at 57.6 kHz (12X bit rate) and the result filtered with an IIR filter based on a single-pole highpass at 224 Hz.   The upper trace -- the result of all of the filtering -- shows that the two highpass filters severely distort the signal.  In particular the flat tops of the long (3-bit) sequences decay almost to zero.  This degree of distortion would erode the bit error performance.  Consequently, a simple highpass filtering scheme to remove low-frequency interference won't work.

    What does appear to work is a filter that determines the approximate DC level of the signal and subtracts it out.  The result of applying this type of filter in combination with an off-chip single-pole highpass at 175 Hz is shown in figure 4.2.

Figure 4.2 -- Combined Single-Pole and Subtraction Receive Filters
Lower Trace = Input, Upper Trace = Filtered

  The dimpled look of the longer pulses (upper trace) is caused by the subtraction filtering.  Except for these and a slight slant in the tops of the pulses, the upper waveform is now very similar to the lower (input).  The subtraction filter works as follows.  A number N of signal samples is taken so that half are ahead of the sample to be filtered and half are behind it.  The minimum and maximum of the N samples are found.   The mean of these two numbers is found and subtracted from the current signal sample.  N is ideally short so that the value being subtracted is representative of the current sample.  But it must be long enough that it catches both positive- and negative-going portions of the desired NRZ signal.  A sample rate of 12X bit rate means that a given positive- or negative-going part of the NRZ signal can be no more than 36 samples.  Therefore, an N of about 40 seems optimal.

    The effectiveness of the combined highpass filters in removing interference is illustrated in figure 4.3.  Here, the filter is applied to a (signal + interference).  The interference is a sine wave at 25 Hz and having an amplitude 28 times the signal.  This is twice the maximum expected level of interference.  To allow convenient viewing, the input (signal + interference) in the bottom trace has been scaled down by a factor of 25.  The desired signal is barely visible as a slight ripple on the lower trace.  It is clear that the filter removes the interference without significantly distorting the signal.  The upper trace remains nearly as good as that of figure 4.2, in which there was no added interference.

Figure 4.3 -- Highpass Receive Filters Applied To Signal With Interference

    Another method of dealing with low-frequency interference also showed some promise in simulations.  First, simple linear filters are used to remove the low-frequency interference.  This leads to the result of figure 4.1.  Then a form of decision-feedback-equalization is used to correct the waveform of figure 4.1.

4.2    Master Transmit Highpass

    A source of distortion arises when a low-impedance Master is connected to the network through a relatively small coupling capacitor.  It is indicated in the document on FASTHART requirements (Click here to view.), that this highpass coupling can have a corner frequency as high as 468 Hz.  The resulting distortion is given in the form of an eye diagram in figure 4.4.   The diagram was produced using a combination of a 2 ufd coupling capacitor and a 170 ohm network resistance.  The transmitted signals prior to network coupling were all trapezoidally shaped and had a swing from -1 to +1.

Figure 4.4 -- Master Transmit Eye Diagram With 468 Hz Corner

The eye diagram shows that the jitter in the zero-crossings is about 1/3 of a bit time and that in some of the eyes the signal has almost drooped down to the zero line.   This makes it difficult for the proposed method to meet error requirements.

    An approach to fixing the distortion is an equalizer at the transmitter.  Since the network resistance and the coupling capacitor can both vary, there is no single equalizer that satisfies every requirement.  The network resistance varies from 170 ohm to 600 ohm.  This is external to the device and can't be controlled.  But the coupling capacitor is part of the device.  This suggests that a compromise equalizer with an adjustment based on the coupling capacitor is possible.  The modem would be programmed in some way to perform an equalization based on the selected coupling capacitor and on a resistance midway between the extremes of 170 ohm and 600 ohm.  The equalizer is set up to have a transfer function of the approximate form