On-Line Data Sheet for 20C15

By Analog Services, Inc.

(Corrected on  4-18-01)

Description     |       Pinout        |         Operation       |         Parameters          |           Circuits        |       Package

The 20C15 HART Modem IC is made by LSI Logic.   Unfortunately, they provide only paper copies of the 20C15 data sheet.  It does not show up on their web site (at www.lsilogic.com).    We have created here our own data sheet for the 20C15 to make it easier for HART designers to get this information on the internet.  To purchase the 20C15 integrated circuit or to get a complete copy of the LSI Logic data sheet, contact LSI Logic at

LSI Logic Corp.
1551 McCarthy Blvd
Milpitas, California 95035
800.433.8778 (in the United States)
408.433.8000 (outside the United States)
Fax 408.433.8989

Description

    The 20C15 is a low-power, single-chip, 1200 bps modem specifically designed to satsify HART Protocol requirements.   It contains nearly all of the circuitry needed to add HART communication capability to analog 4-20 mA field instruments.  It is specified for use at supply voltages of 3.3 volt and 5.0 volt and over the industrial process control temperature range of -40 C to 85 C.  For lowest possible power consumption the modulator portion of the chip is shut down while the demodulator is operating and vice-versa.  A crystal or ceramic resonator operating at 460 kHz may be used with the chip to generate a 460 kHz clock.   Or a 460 kHz clock may be supplied to one of the 20C15 pins.  An external bandgap voltage reference is required to set up reference voltages and the device operating current.  The 20C15 includes transmit waveshaping and part of the receive filtering required by HART.  The 20C15 is supplied in a 28-pin PLCC package.

 

Pinout

Pin Number

Name

In/Out

Description

Comment

1,5,7,8,9,14     Test Connect To Ground
2,3,4,25,28     Test Leave Open
6 /RESET In Reset (Low To Reset) Connect To R & C
10 OTXA Out Transmit Out  
11 IAREF In Reference Voltage Connect to 1.235 volt for 3.3 volt supply,
Connect to 2.5 volt for 5.0 volt supply.
12 ICDREF In Carrier Detect Reference
Voltage
Set at 80 mV below IAREF
13 OCBIAS   Operating Current Set Connect 500k to gnd for 3.3 volt supply,
Connect 1 Meg to gnd for 5.0 volt supply.
15,22     Power Pin Connect to 3.3 volt or 5.0 volt.
16 IRXA In Input to Receive Gain Stage See Circuits
17 ORXAF Out Output from Rcv Gain Stage Low Impedance Point
18 IRXAC In Receive Filter Continued  
19 OXTL Out Crystal Oscillator Output 460 kHz
20 IXTL In Crystal Oscillator Input Or External Clock Drive
21     Ground  
23 INRTS In Request-to-Send Selects between XMIT and RCV
24 ITXD In Transmit Data  
26 ORXD Out Receive Data  
27 OCD Out Carrier Detect  

Operation

    Modulator (Transmit):

   The modulator is operating (and the demodulator is shut down) whenever /RTS (INRTS) is low.  When TXD (ITXD) is high the modulator output at TXA (OTXA) will be a trapezoidally shaped wave at nominally 1200 Hz.  When TXD is low the modulator output is nominally 2200 Hz.  TXA (OTXA) is usually AC-coupled to an amplifier or buffer stage.

    The output voltage levels at TXA depend on the reference voltage applied at IAREF.  Let VQ, VMIN, and VMAX be as defined in figure 1.

ds20c_1.gif (2308 bytes)

Figure 1

That is, VQ is the quiescent (no modulation) voltage at TXA, and VMAX - VMIN is the pp signal voltage swing.  VQ, VMIN, and VMAX are given by

ds20c_2.gif (1139 bytes)

wpe10.gif (1176 bytes)

wpe11.gif (1185 bytes)

 

where VREF is the voltage at pin IAREF.  For VREF = 1.235 volt,   VQ is 0.5 volt and the signal swings from 0.25 volt to 0.75 volt.  In a HART Master this is the correct pp voltage to be applied to the network.  But the OTXA pin does not have enough drive capability to drive a HART network directly.  A buffer amplifier is usually needed.  In a field instrument, the 0.5 volt pp OTXA output is usually converted to 1 mA pp.

   

    Demodulator (Receiver):

   The demodulator is operating (and the modulator is shut down) whenever /RTS (INRTS) is high.  The received signal is first applied to a bandpass filter.  Part of this filter is off-chip.   This is necessary to reduce interference to a level that is within the 20C15 supply rails.  The bandpass filter consists of a 4-pole highpass filter and a single-pole lowpass.  When used with the suggested passive components the overall filter has a gain of 1.6 in the passband.  Other pins that are part of the receive filter are IRXA, ORXAF, and IRXAC.

    The filter output is applied to two comparators -- one to slice the signal and produce a logic-level version of the received FSK and a second to act as a carrier detect.  The reference for the first comparator is the reference voltage applied at IAREF.  The reference for the second comparator is applied at ICDREF and is normally set to be 80 mV below the level at IAREF.    The carrier detect comparator is therefore tripped if the filter output swings low by 80 mV peak or more.  Or, since the filter has a passband gain of 1.6, the carrier detect comparator will trip if the input swings by 50 mV peak (100 mV pp) or more.  These values are chosen to satisfy the HART requirement that the carrier detect be OFF for input signals < 80 mV pp and ON for input signals > 120 mV pp.

    Logic circuits following the carrier detect comparator are used to decide whether carrier is present.  If the input has sufficient amplitude to trip the carrier detect comparator on each of 3 or 4 consecutive cycles, then carrier is present and OCD goes high.  Once carrier is present, if  the input signal fails to trip the comparator for a time of about 3 or 4 cycles, then carrier is no longer present and OCD goes low.

    The logic-level FSK out of the first comparator is applied to a logic block that generates a high level if a frequency below 1700 Hz is present and a low level if a frequency above 1700 Hz is present.  The output of this logic block is gated with OCD to form the output RXD (ORXD).   If carrier is not present the RXD output is always low.  If carrier is present, then RXD equals the output of the logic block.

    RXD (ORXD) is normally connected to a UART.  The UART sees a low level as an assertion of RXD.  Therefore, when no carrier is present (no reception occuring) RXD is asserted.  In some cases this will appear to be an extra character at the end of a message.  The software that services the UART must handle this condition appropriately.

 

    Clock:

    A 460.8 kHz clock is required.  This can be generated by connecting a crystal or ceramic resonator across pins OXTL and IXTL (see Circuits).  An external clock source can also be used.  Connect the external source to OXTL and connect IXTL to ground.

 

Parameters

    Clock:  460.8 kHz, Tolerance 1%.

    Power Supply Current:    400 uA max.  (3.3 volt supply),  600 uA max.   (5.0 volt supply).
        (NOTE:  This is the current during receive.  It is about 100 uA to 200 uA less during transmit.
         This can sometimes be used to advantage.)

    Operating Temperature Range:    0 C to 70 C.  (NOTE:  This would seem to preclude using
        this part in industrial control applications, which usually require -40 C to 85 C.  However, this
        specification is apparently the result of problems in testing the part outside of 0 C to 70 C; and
        doesn't reflect the part's true capability.   It is designed for and is being widely used in equipment
        specified for -40 C to 85 C.)

    Reset Minimum Pulse Time:   2 microsecond.

    Transmit Output Drive Capability:   Needs minimum of 30 kohm.

 

Circuits

    Field Instrument, 3.3 Volt Supply:

wpe8.gif (15387 bytes)

Figure 2

    Field Instrument, 5.0 Volt Supply:

wpe9.gif (15381 bytes)

Figure 3

Package

wpe16.gif (2694 bytes)

Figure 4

Package -- 28 Pin PLCC

 

 


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