About HART -- Prolog & Table of Contents
By Analog Services, Inc.
Revised 8-9-99
Prolog
HARRY: (looking at clipboard) "We're scheduled to
start the ACME Company batch at 11:00 A.M. on
Wednesday. We'll have to re-range 17 flow
transmitters and two pH meters. I'll get the
technicians out to the field first thing
tomorrow. It'll probably take 'em a whole day
because some of the transmitters are impossible
to get to."
SALLY: (without looking up from CRT display)
"Thanks Harry, but you're forgetting that we
retrofitted to HART transmitters last year. We
can re-range them right here. It'll just take a
few minutes."
Introduction
Overview:
HART and the Conventional Process Loop
Signaling
HART Process Transmitter Block Diagram
Building Networks
Protocol
Addressing
Conclusion
Why So Slow?
What's In A Bell-202 Standard?
Process Receiver
Other Books About HART?
Alternatives to HART
Table of Current HART PublicationsA Caveat: HART and Current Consumption
Modem Sources
HART Library Software For PC
HART and PCs
Timing is Everything
The Beginning, End, Gaps, and Dribbles
Start-Up Synchronization In HART
Slave Receive Algorithm
Data Compression
Device Description Language
Slave Development Steps
Addressing Problems, Slave Commissioning, and Device Database
Bell-202: Bad News in Europe
Grounding and Interference
HART and Intrinsic Safety
HART and CE Mark
Electrical Measurement of a HART Network
Isolating A Non-Isolated Modem
Troubleshooting: What To Do When "It Just Won't Talk"
HART Repeater
HART Gateways and Alternative Networks
PC as Gateway
DeviceNet to HART
HART Over RS485/RS232
Combined Baseband and Conventional HART
Telecom HART
Fiber Optic HART
Single Modem/Multiple Point-to-Point
Wireless HARTEquation Describes CPFSK
Generating HART Signal With MATLAB
OSI Model
HART Network Circuit Models
HART Signal Power Spectral Density
Cable Effects
HART Message Errors
HART Experimental Error Rates
How Fast?
List of Tables
Table 1.1 -- Parts of HART Message
Table 1.2 -- HCF Publications
Table 2.1 -- Timer Values
Table 2.2 -- HART and DeviceNet
Comparison
Table 3.1 -- Cable Capacitances
Table 3.2 -- Comparison Between SPICE Model and Simple Model
Table 3.3 -- Comparison of Measured and Calculated Output Voltage
List of Figures
Figure 1.1 -- Conventional Process Loop
Figure 1.2 -- Process Loop With HART Added
Figure 1.3 -- HART Carrier Burst
Figure 1.4 -- Separation of Analog and HART (Digital) Signals
Figure 1.5 -- HART Signal Path
Figure 1.6 -- HART Character Structure
Figure 1.7 -- Illustration of Continuous Phase FSK
Figure 1.8 -- Typical HART Process Transmitter Block Diagram
Figure 1.9 -- HART Network With Multi-Dropped Field Instruments
Figure 1.10 -- HART Network Showing Free Arrangement of Devices
Figure 1.11 -- Single Cable With Multiple HART Networks
Figure 1.12 -- Carrier Bursts During HART Transaction
Figure 1.13 -- Unique Identifier and Long Address
Figure 1.14 -- Process Receiver Loop Circuitry
Figure 2.1 -- Available Operating Current With HART
Figure 2.2 -- Master Alternation
Figure 2.3 -- Master Alternation With No Slave Response to Master 1
Figure 2.4 -- Alternating Masters with Master 2 Failing to Recognize Slave Response to
Master 1
Figure 2.5 -- Start-Up Synchronization
Figure 2.6 -- Slave Receive Algorithm
Figure 2.7 -- HART Circuit Showing Ground Potential Difference
Figure 2.8 -- Equivalent Circuit for Effect of Ground Potential Difference
Figure 2.9 -- Simplest IS Arrangement
Figure 2.10 -- More Complex IS Arrangement
Figure 2.11 -- Most Complex IS Arrangement
Figure 2.12 -- RF Circulating Current in Process Instrument
Figure 2.13 -- Isolating HART Master
Figure 2.14 -- Repeater Block Diagram
Figure 2.15 -- Direction State Machine
Figure 2.16 -- Using PC As Gateway
Figure 2.17 -- Baseband HART Using RS232/RS485
Figure 2.18 -- Super HART Network Using RS485
Figure 2.19 -- Illustration of Using Telephone Network for HART
Figure 2.20 -- Block Diagram of Telecom/HART Interface
Figure 2.21 -- Fiber Optic HART Network
Figure 2.22 -- Single Modem Coupled To Multiple Point-to-Point Networks
Figure 2.23 -- Coupler
Figure 3.1 -- Example of HART Signal Generation
Figure 3.2 -- HART Transmitter Showing Approximate OSI Boundaries
Figure 3.3 -- Cable Section Model
Figure 3.4 -- 4-Pair Circuit Model
Figure 3.5 -- Simple Model
Figure 3.6 -- Newer Network Circuit Models
Figure 3.7 -- HART Power Spectrum
Figure 3.8 -- Measured HART Power Spectrum
Figure 3.9 -- HART PSD With and Without StartStop Bits
Figure 3.10 -- HART PSD With Sinusoidal and Trapezoidal Shaping
Figure 3.11 -- HART Cable Length
Figure 3.12 -- Crosstalk Path in Multi-Pair Cable
Figure 3.13 -- HART Message as Bit Matrix
Figure 3.14 -- Bit Matrix That Will Cause UME
Figure 3.15 -- Plot of BER v. (Noise + Crosstalk)
Continue to Part 1: Preliminaries
Continue to Part 2: Practical Stuff
Continue to Part 3: Ponderous Stuff
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E-Mail: stevea@analogservices.com